Latch is not that BAD - Latch Vs Flip-flop

Instead of saying “avoid latches whenever possible”, we can say "don't use latches unless you know you need them". For me, both statements are similar but, my point is that, Latch itself will not say “I'm not that bad”.

Being in limelight, Latches are about something being inferred in your design which need attention. Now a days, almost all the EDA tools help designers to pin-point the existence of latches in their design as a ‘must to know’ information. And then, designer is responsible to correct if the latch usage is unintentional, which could be easily happened due to poor RTL coding practices as well. Once the latch existence is acknowledged at Synthesis level, then the downstream tools follows those conventions. This statement is fine with ASIC, but the latch existence is not recommended in FPGA. It would be fine to say “FPGA tools works more accurate in timing the register based designs”

Once you have decided to use latches for your design, ensure that the enable signal is stable and valid data is being captured in the latch, to avoid unstable states in your design. Yesterday, I got my old notes, prepared during my masters, and thought to put them together for everyone’s reference.

Here is the comparison between Latch Vs Flip-flop...

Latch	Flip-Flop
Latch is transparent – because input is directly connected to output when enable is high	Flip-flop is a pair of latches (master and slave flop)
Soft barrier -  a signal can’t propagate through until the clock is high	Hard barrier -  the signal only propagates through on the rising/falling edge
Less Area (less gates)	More Area (more gates)
Less Power (less gates)	More Power (more gates)
Fast (used in high speed designs)	Slow
Require more tool manipulation and more hand-calculations to verify that they meet timing	Easy to check design timing using Static Timing Analysis (STA) tools
Cycle-borrowing to gain more setup time on the next register stage, as long as each loop completes in one cycle To meet the timing in the design. Designers consider latch to adjust timing mismatch.	Data launches on one rising edge, so it must setup before next rising edge. If it arrives late, system fails. If it arrives early, time is wasted due to hard edges in Flops
For ASICs with large clock skew, latches have substantial benefits for reducing the clock period	Even for the high speed pulsed flip-flops with  zero setup time, as they are not transparent, the impact of the clock skew is not reduced
level-sensitive latches reduce the impact of inaccuracy of wire load models and process variation.	Flip-flops demands for the highly accurate wire load model and process
In DFT, Latches needed as a lockup state at the clock domain crossings in the scan chain to avoid unpredictable behavior	In DFT, use flops that can be scanned (controllable and observable)
In FPGA, level-sensitive transparent latches should be avoided in FPGAs	In FPGA, edge-sensitive flip-flops is used exclusively. FPGA tools algorithm is implemented in such way.
Circuit analysis is complex. You may see last minute timing mismatch surprises at the implantation stage.	Circuit analysis is easy
High-speed microprocessor designs typically use master-slave latches instead of flip-flops so that logic can be added between the rising and falling clock edges. The master-slave flops are sometimes referred to as LSSDs (Level Sensitive Storage Devices). Most of these companies have written their own specialized STA tools to verify latch-based designs. (this statement is copied from a blog on SystemVerilog)	The most commonly used flop in the design world is D type flip-flop.
For non-timing-critical configuration registers, latches work great, due to fewer gates and less power consumption	For non-power aware design, Flip flops are proffered over Latches
Latch is an asynchronous block. Therefore you must ensure, that the combinational functions which generate input signals for the latch are race-free. Otherwise they may generate glitches, which may be latched, causing hazards in your system.	A flip-flop, on the other hand, is edge-triggered and only changes state when a control signal goes from high to low or low to high